Carbon nanotubes possess extraordinary electronic properties that are attractive for high-speed and high-performance circuits. One of the major challenges in utilizing devices and complex circuits involving carbon nanotubes lies in the incompatibility of the carbon nanotube growth conditions and the process limitation of current complementary metal-oxide-semiconductor (CMOS) technology. For example, chemical vapor deposition (CVD) grown carbon nanotubes require a growth condition of at least 600° C. for producing high quality nanotubes, which exceeds the temperature capacity of about 350° C. to about 400° C. for CMOS processes.
One possible solution to work around this temperature limitation is to deposit pre-formed carbon nanotubes on the substrate from a solution. However, during the subsequent processing, the deposited carbon nanotubes may be destroyed via oxidation and the properties of the carbon nanotubes may also be altered due to surface treatments.
Another practical challenge of realizing integrated circuits based on carbon nanotubes is the alignment of carbon nanotubes with the rest of the circuit components. While there has been much progress in controlling the growth orientation and/or the deposition location of nanotubes, their alignment with the rest of the circuits has not been addressed.
Therefore, techniques for three-dimensional carbon nanotube-based integrated circuit device integration would be desirable.